Electronic image sensors are widely used in a variety of electronic cameras and scanners. Historically, most of these sensors have been implemented as charge-coupled devices (CCD). A CCD converts photons captured in individual picture elements (pixels) into electrical charge. In a CCD, complicated clock voltages and high voltage potentials are required to transfer the electric charge that results from the absorption of photons out of the pixel. More recently CMOS active pixel sensors (APS) have been developed. A CMOS active pixel sensor is preferred over a CCD because the circuit that generates the requisite timing signals can be integrated on the same chip with the pixel circuit and because a CMOS active pixel sensor operates at a lower voltage level and consumes less power than a CCD. In a CMOS APS each pixel contains a light-sensitive element, such as a photodetector that can be implemented as a photodiode (pd), and several transistors integrated on the same substrate, referred to as being integrated on the same “chip.” The chip comprises multiple layers of semiconductor material formed over a substrate. The elements of the pixel are formed by growing or depositing layers of semiconductor material over the substrate and selectively etching the layers of semiconductor material to form the elements. The pixels are typically arranged in an array having rows and columns to form an image sensor.
In one common implementation, the pixel contains a photodiode and three transistors. Such an implementation is shown in FIG. 1. FIG. 1 is a schematic view of a conventional CMOS pixel 1. The pixel 1 comprises a photodiode 2 and transistors 4, 6 and 7. Each of the transistors 4, 6 and 7 can be a CMOS field effect transistor (CMOSFET). The transistor 4 functions as a reset switch, the transistor 6 functions as a source follower buffer amplifier, referred to as a “source follower,” and the transistor 7 functions as a row select switch. The reset transistor 4 is used to initialize the photodiode 2 in a reverse-biased state by coupling the photodiode 2 to voltage source Vdd when the reset transistor 4 is on via a signal on the gate terminal 8. The source follower transistor 6 buffers the output signal of the photodiode 2, and the row select transistor 7 is responsive to a row select signal and connects the output of the pixel on line 11 to a column line that is connected to a column processing circuit (not shown).
One disadvantage of a CMOS APS is that the light sensitive area of the pixel (the light capturing area of the photodiode) is only a small fraction of the total area of the pixel. This disadvantage can be overcome by locating the photodiode in a layer other than the layer in which the transistors are formed, thus maximizing the light capturing area of the photodiode. One way to create such a pixel is to form the transistors in one or more layers of crystalline silicon and then form a layer of α-Si:H (hydrogenated amorphous silicon) over the layer of crystalline silicon in which the transistors are formed. The photodiode is then formed in the layer of α-Si:H. Photodiodes that are formed in this layer of α-Si:H are almost as large as the overall pixel dimensions, and therefore have a larger light sensitive area. A simplified layer structure that includes the transistors and photodiode of FIG. 1 is shown in FIG. 2. The layer structure 20 includes a layer 21 of crystalline silicon in which the transistors 4, 6 and 7 are formed and a layer of hydrogenated amorphous silicon 22 in which the photodiode 2 is formed.
FIG. 3 is a schematic diagram illustrating a simplified image sensor 30 formed using a plurality of the pixels of FIG. 1. The image sensor 30 includes a pixel array 32 that comprises a plurality of pixels 1 arranged in a row and column format. All of the pixels in a row are coupled to a row select line, an exemplary one of which is illustrated using reference numeral 34. All of the pixels in a column are coupled to a common column line, an exemplary one of which is illustrated using reference numeral 36. A reset line is coupled to each pixel in each row, and is omitted for simplicity. In this manner, a row select signal supplied over a row select line by circuitry that is not shown can be used to activate the pixels in a particular row. In response to the row select signal, each of the pixels in a row reads out accumulated charge via its respective column line.
FIG. 4 is a schematic diagram illustrating the operating cycles of two rows of pixels of FIG. 3. For example, during a reset period 41 the pixels in row n will be reset by turning on the reset transistor 4 (FIG. 1) in each pixel. After the reset period 41, the photodiode 2 collects light and accumulates charge during the accumulate period 42. At the end of the accumulate period 42, the accumulated charge is read out of each pixel 1 (FIG. 1) in row n during read period 44 by turning on the row select transistor 7 (FIG. 1) of the pixel. Activating the row select transistor 7 couples the output of the photodiode 2 to a corresponding column line, such as column line 36 in FIG. 3. Although omitted for simplicity, each column line in FIG. 3 is coupled to circuitry for sampling and holding the value of the charge from each pixel. The reset period 41, accumulate period 42 and the read period 44 comprise one operating cycle, also referred to as a “row period,” of the pixels in row n. The row period is the time required to read one row of pixels. A frame period is the time required to read all rows in an array.
Unfortunately, while forming the photodiode in a layer of hydrogenated amorphous silicon increases the capture area of the photodiode, the hydrogenated amorphous silicon layer leads to a condition in which some of the light-induced charge in the photodiode cannot be removed during one operating cycle of the pixel. Dangling bonds present in the hydrogenated amorphous silicon and trap charge in the photodiode. The dangling bonds constitute what are referred to as “charge traps” in the photodiode. Hydrogenation of the amorphous silicon reduces the number of dangling bonds by attaching hydrogen atoms to them, but some dangling bonds remain. When the photodiode is exposed to photons of light, electron-hole pairs are created and the charge of the electron is stored in the photodiode. If the photodiode has many of these so called “charge traps,” some portion of the electric charge in the photodiode is trapped in the charge traps and will not be released in a single operating cycle. Because the trapped electric charge cannot be released from the photodiode in a single operating cycle, the electric charge is released over a period of successive operating frames.
When combined over an image sensor having many pixels, the effect of electric charge trapped in the photodiode and released over successive operating frames gives rise to a condition referred to as “image lag.” When an image sensor suffers from image lag, information from one frame will persist in many subsequent frames. This phenomenon is most noticeable when the image sensor is implemented in a camera. When the camera pans across a bright object in an otherwise dark scene, image lag manifests as a bright trail in an otherwise dark image.
Therefore, it would be desirable to minimize the effect of electric charge trapped in a CMOS photodetector.